The FET is an important electrical switching device in very large scale integrated (VLSI) circuits. Such circuits may contain hundreds of millions of FETs on a single semiconductor chip. Such chips typically measure less than 1 cm on a side. The physical size (i.e. the lateral dimensions) of the FET device and the ease of electrically interconnecting a plurality of FETs are important factors in determining how closely devices may be packed into a given chip area. Thus, the degree of integration is in part determined by the device packing density.
The demands for higher performance MOSFET require MOSFETs to have shorter channel lengths for higher current drive. Accordingly, work continues for providing new lithographic procedures for yielding the minimally smallest structure for a given lithographic features size without significantly increasing the complexity of the fabricating process. For instance, very short channel MOSFET devices can be built by using sub-lithographic technique such as phase-edge and hybrid-resist lithography to define a device-gate. Particularly, hybrid-resist lithography is very attractive because of its superior line width control over any other lithographic technique. However, these techniques require trimming of a loop to define a straight device gate. Trimming requires an extra trim mask and trim-etch process and also requires an extra area for trim mask. As the device channel length becomes shorter, the gate width narrows. The narrowing of the gate width, in turn, makes it difficult to process the gate for achieving low resistance such as by salicidation.